Design of High-Performance Microprocessor Circuits

Title: Design of High-Performance Microprocessor Circuits
Author: Anantha Chandrakasan (Editor), Frank Fox, William J. Bowhill (Editor)
ISBN: 078036001X / 9780780360013
Format: Hard Cover
Pages: 578
Publisher: IEEE
Year: 2001
Availability: 45-60 days

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This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola.
Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth :

Architectural constraints of CMOS VLSI design
Technology scaling, low-power devices, SOI, and process variations
Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units
Latches, clocks and clock distribution, phase-locked and delay-locked loops
Register file, cache memory, and embedded DRAM design
High-speed signaling techniques and I/O design
ESD, electromigration, and hot-carrier reliability
CAD tools, including timing verification and the analysis of power distribution schemes
Test and testability

Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

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Preface

Part 1 : Overview
Chapter 1 : Impact of Physical Technology on Architecture

Part 2 : Technology Issues
Chapter 2 : CMOS Scaling and Issues in SUB-0.25µm Systems
Chapter 3 : Techniques for Leakage Power Reduction
Chapter 4 : Low-Voltage Technologies
Chapter 5 : SOI Technology and Circuits
Chapter 6 : Models of Process Variations in Device and Interconnect

Part 3 : Circuit Styles for Logic
Chapter 7 : Basic Logic Families
Chapter 8 : Issues in Dynamic Logic Design
Chapter 9 : Self-Timed Pipelines
Chapter 10 : High-Speed VLSI Arithmetic Units : Adders and Multipliers

Part 4 : Clocking
Chapter 11 : Clocked Storage Elements
Chapter 12 : Design of High-Speed CMOS PLLs and DLLs
Chapter 13 : Clock Distribution

Part 5 : Memory System Design
Chapter 14 : Register Files and Caches
Chapter 15 : Embedded Dram

Part 6 : Interconnect and I/O
Chapter 16 : Analyzing On-Chip Interconnect Effects
Chapter 17 : Techniques for Driving Interconnect
Chapter 18 : I/O and ESD Circuit Design
Chapter 19 : High-Speed Electrical Signaling

Part 7 : Reliability
Chapter 20 : Electromigration Reliability
Chapter 21 : Hot Carrier Reliability

Part 8 : CAD Tools and Test
Chapter 22 : Overview of Computer-Aided Design Tools
Chapter 23 : Timing Verification
Chapter 24 : Design and Analysis of Power Distribution Networks
Chapter 25 : Testing of High-Performance Processors

Index