Title: Electronic Design Automation for Integrated Circuits Handbook, 2nd Edition (2 Volume Set) Author: Grant E. Martin, Igor L. Markov, Louis K. Scheffer, Luciano Lavagno ISBN: 1032339985 / 9781032339986 Format: Soft Cover Pages: 1472 Publisher: CRC Press Year: 2022 Availability: 2 to 3 weeks
Description
Contents
Comprised of two volumes, Electronic Design Automation for Integrated Circuits Handbook, Second Edition addresses all major areas of EDA for integrated circuits (ICs). Chapters contributed by leading experts authoritatively discuss an array of topics ranging from system design to physical implementation.
New to This Edition:
Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs
Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography
New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, back-annotating system-level models, 3D circuit integration, and clock design
Offering improved depth and modernity, Electronic Design Automation for Integrated Circuits Handbook, Second Edition – Two-Volume Set provides a valuable, state-of-the-art reference for EDA students, researchers, and professionals.
Part I : Introduction
Chapter 1 : Overview Chapter 2 : Integrated Circuit Design Process and Electronic Design Automation Chapter 3 : Tools and Methodologies for System-Level Design Chapter 4 : System-Level Specification and Modeling Languages Chapter 5 : SoC Block-Based Design and IP Assembly Chapter 6 : Performance Evaluation Methods for Multiprocessor System-on-Chip Design Chapter 7 : System-Level Power Management Chapter 8 : Processor Modeling and Design Tools Chapter 9 : Models and Tools for Complex Embedded Software and Systems
Part II : System-Level Design
Chapter 10 : Using Performance Metrics to Select Microprocessor Cores for IC Designs Chapter 11 : High-Level Synthesis
Part III : Microarchitecture Design
Chapter 12 : Back-Annotating System-Level Models Chapter 13 : Microarchitectural and System-Level Power Estimation and Optimization Chapter 14 : Design Planning Chapter 15 : Design and Verification Languages Chapter 16 : Digital Simulation Chapter 17 : Leveraging Transaction-Level Models in an SoC Design Flow
Part IV : Logic Verification
Chapter 18 : Assertion-Based Verification Chapter 19 : Hardware-Assisted Verification and Software Development Chapter 20 : Formal Property Verification
Part V : Test
Chapter 21 : Design-for-Test Chapter 22 : Automatic Test Pattern Generation Chapter 23 : Analog and Mixed-Signal Test
Part VI : RTL to GDSII, or Synthesis, Place, and Route
Chapter 24 : Design Flows Chapter 25 : Logic Synthesis Chapter 26 : Power Analysis and Optimization from Circuit to Register-Transfer Levels Chapter 27 : Equivalence Checking Chapter 28 : Digital Layout: Placement Chapter 29 : Static Timing Analysis Chapter 30 : Structured Digital Design Chapter 31 : Routing Chapter 32 : Physical Design for 3D ICs Chapter 33 : Gate Sizing Chapter 34 : Clock Design and Synthesis Chapter 35 : Exploring Challenges of Libraries for Electronic Design Chapter 36 : Design Closure Chapter 37 : Tools for Chip-Package Codesign Chapter 38 : Design Databases Chapter 39 : FPGA Synthesis and Physical Design
Part VII : Analog and Mixed-Signal Design
Chapter 40 : Simulation of Analog and RF Circuits and Systems Chapter 41 : Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits Chapter 42 : Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A Survey
Part VIII : Physical Verification
Chapter 43 : Design Rule Checking Chapter 44 : Resolution Enhancement Techniques and Mask Data Preparation Chapter 45 : Design for Manufacturability in the Nanometer Era Chapter 46 : Design and Analysis of Power Supply Networks Chapter 47 : Noise in Digital ICs Chapter 48 : Layout Extraction Chapter 49 : Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation
Part IX : Technology CAD
Chapter 50 : Process Simulation Chapter 51 : Device Modeling: From Physics to Electrical Parameter Extraction Chapter 52 : High-Accuracy Parasitic Extraction